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Semiconductor memory device having a capability for controlled activation of sense amplifiers

机译:具有控制读出放大器的激活能力的半导体存储器件

摘要

A semiconductor memory device includes a memory cell array (42) in which a number of sense amplifiers are provided, a plurality of segmented drive lines (43i, 43i+1) each connected to a group of sense amplifiers for driving the same, each of the segmented drive lines being formed of first and second drive line segments (44i, 44i+1, 45i, 45i+1) forming a pair, and a number of trunks (50(i+1)/2, 51(i+1)/2, 58(i+1)/2, 58(i+1)/2) for supplying electric power to the segmented drive lines. Each of the trunks includes a first conductor strip extending from a first side of the memory cell array toward a second side for connection to a plurality of the first drive line segments upon crossing the same, and a second conductor strip extending from the second side of the memory cell array toward the first side for connection to a plurality of the second drive line segments upon crossing the same. The first and second conductor strips have distal end parts having a reduced width (W₂) and a mutually complementary shape, such that the first and second conductor strips are disposed to form a straight strip having a substantially constant width (W₁) throughout the memory cell array.
机译:半导体存储器件包括:其中设置有多个读出放大器的存储单元阵列(42),多条分段驱动线(43 i ,43 i + 1 )分别连接到一组用于驱动它们的读出放大器,每个分段驱动线由第一和第二驱动线段(44 i ,44 i + 1 ,45 i ,45 i + 1 )形成一对,以及多个中继线(50 (i + 1)/ 2 ,供供使用的51 (i + 1)/ 2 ,58 (i + 1)/ 2 ,58 (i + 1)/ 2 )分段驱动线的电力。每个主干包括:第一导体带,第二导体带从存储单元阵列的第一侧向第二侧延伸,以在交叉时连接到多个第一驱动线段;以及第二导体带,从第二存储单元的第二侧延伸。存储器单元阵列朝向第一侧,以便在交叉时连接到多个第二驱动线段。第一和第二导体条的末端部分具有减小的宽度(W 2)和相互互补的形状,从而第一和第二导体条被设置为形成在整个存储单元中具有基本恒定的宽度(W 1)的直条。数组。

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