A variable accuracy indirect addressing scheme for SIMD multi-processors and apparatus implementing same

摘要

Described is a parallel processing architecture following the Single Instruction stream Multiple Data stream execution paradigm where a controller element (18) is connected to at least one processing element (10) with a local memory (38) having a local memory address shift register (46) adapted to receive and retain therein a globally broadcast memory base register address value received from the controller element (18) for use by the processing element for access and transfer of data between the processing element (10) and its respective local memory (38). A computer architecture for implementing indirect addressing and look-up tables includes a processing element shift register (44) associated with the at least one processing element (10) and adapted to receive and retain therein a local memory offset address value calculated or loaded by the associated processing element (10) in accord with a first predetermined set of instructions. The processing element shift register (44) transfers its contents bitwise to the local memory shift register (46) of the local memory (38) associated with the processing element (10), with the bit value of the most significant bit position being sequentially transferred to the least significant bit position of the local memory shift register (46) in accord with a second predetermined set of instructions.