HIGH-SPEED VOLTAGE BALANCING FOR COMPLEMENTARY DATA LINE FOLLOWING WRITE CYCLE OF MEMORY CIRCUIT

摘要

PROBLEM TO BE SOLVED: To perform the fast balancing of a complementary data line following a write cycle by combining the disconnection of a high data wire from a VDD and the activation of a balanced transistor. ;SOLUTION: A signal on an I/O circuit When logic 1 is written and the gate terminals of pull-up and pull-down transistors(TR) 300 and 304, and 302 and 306 coupled with it are pulled low; and the write cycle is finished and a data line balancing process is started. When logic 0 is written, a true data line I/O is pulled low and its complementary line, the inverse of I/O is still VDD. Thus, an I/O circuit individually controls the gate terminals of TRs 3090 and 304, and 302, and 306 connected to a data line. A data line balancing time is obtained after a write cycle which can make a read cycle faster than following one by individually controlling ON/OFF timing so that a high data line voltage is lowered.;COPYRIGHT: (C)1996,JPO