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Fast voltage equilibration of complementary data lines following write cycle in memory circuits
Fast voltage equilibration of complementary data lines following write cycle in memory circuits
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机译:存储电路中的写入周期后,互补数据线的快速电压平衡
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摘要
A method and a circuit for fast equilibration of complementary data lines in memory circuit following a write cycle. The circuit of the present invention separately controls the on/off timing of pull-up and pull-down transistors coupled to the data lines to obtain faster equilibration. In one embodiment incorporating an equilibration transistor between the data lines, the pull-up transistor coupled to the high data line is momentarily turned off after a write cycle, to allow the voltage on the high data line to drop all the way down to the voltage on the recovering low data line to reduce equilibration delay.
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