The high-speed voltage balancing circuit of the complementary data line next to the write cycle in the memory circuit

摘要

The present invention relates to a method and circuitry for rapidly equalizing a complementary data line in a memory circuit following a write cycle. The circuit of the present invention includes a pull-up and pull-down circuit coupled to the data line to achieve rapid equalization. The on / off time of the transistor is controlled separately. In one embodiment that combines the balancing transistors between the data lines, the pull-up transistors coupled to the high data lines after the write cycle are sequentially turned on in order to reduce the equilibrium delay so that the voltage on the high data lines is always restored To the voltage that is applied.