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patsuke of integrated circuit device - ji manner

机译:集成电路器件的patsuke-Ji Way

摘要

PURPOSE: To provide a 3D multi-chip package, and its manufacturing method, comprising densely laminated array, of a semiconductor chip that is at least partially interconnected by a plurality of metallized trenches. ;CONSTITUTION: A step, wherein there is provided with an integrated circuit chip 50 comprising a mtallized trench 62 of high aspect ratio, extending from the first surface to the second surface is included. An etching stop layer 53 is provided at the nearest position where the metal trench 62 ends against a semiconductor substrate. Then an integrated circuit device is attached to a carrier 70 so that the surface of a supporting substrate is exposed, and the substrate is made into a layer thinner than an integrated circuit device so that at least some of the metallized trenches are exposed. Thus, an electric contact is, through an exposed metal trench, formed at an active layer 54 of an integrated circuit chip.;COPYRIGHT: (C)1993,JPO
机译:目的:提供一种半导体芯片的3D多芯片封装及其制造方法,其包括紧密层叠的阵列,该半导体芯片至少部分地由多个金属化沟槽互连。组成:步骤,其中包括集成电路芯片50,该集成电路芯片50包括从第一表面延伸到第二表面的高纵横比的金属化沟槽62。蚀刻停止层53设置在金属沟槽62抵靠半导体基板终止的最近位置。然后,将集成电路器件附接到载体70,从而暴露出支撑衬底的表面,并且将该衬底制成比集成电路器件更薄的层,从而暴露出至少一些金属化沟槽。因此,通过暴露的金属沟槽在集成电路芯片的有源层54处形成电接触。;版权所有:(C)1993,JPO

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