Test structure for characterization, the latch-up circuits cmo5.

摘要

TEST STRUCTURE FOR characterization LASTCH-UP IN CMOS CIRCUITS ON A DEVICE THAT ALLOWS DETERMINATION OF DIFFERENT SENSITIVITY AND PROCESSES TECNOLOGICOS GEOMETRIAS UNWANTED PHENOMENON KNOWN TO LATCH-UP. By combining DISPOSITICO PNPN A SENSIBLE, AN INTEGRATED CMOS capacity and strength is achieved IMPLEMENT A ASTABLE oscillator whose output signal allows direct GET THE LATCH-UP CHARACTERISTIC PARAMETERS SIMPLY visualizing using an oscilloscope analog or digital. The structure can be implemented in any CMOS LSI or VLSI TECHNOLOGY, by superimposing a nine LEVELS WITH MASCARA A typical design as presented. The application is in the world of the microelectronics industry.