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Process for the manufacturing of high-density MOS-technology power devices

机译:高密度MOS技术功率器件的制造工艺

摘要

A process for the manufacturing of high-density MOS-technology power devices comprises the steps of: forming a conductive insulated gate layer (8) on a surface of a lightly doped semiconductor material layer (2) of a first conductivity type; forming an insulating material layer (11) over the insulated gate layer (8); selectively removing the insulating material layer (11) and the underlying insulated gate layer (8) to form a plurality of elongated windows (15) having two elongated edges (17) and two short edges (18), delimiting respective uncovered surface stripes (16) of the semiconductor material layer (2); implanting a high dose of a first dopant of the first conductivity type along two directions which lie in a plane transversal to said elongated windows (15) and orthogonal to the semiconductor material layer (2) surface, and which are substantially simmetrically tilted of a first prescribed angle (A1,A2) with respect to a direction (T) orthogonal to the semiconductor material layer (2) surface, the first angle (A1,A2) depending on the overall thickness of the insulated gate layer (8) and of the insulating material layer (11) to prevent the first dopant from being implanted in a central stripe of said uncovered surface stripes (16), to form pairs of heavily doped elongated source regions (6) of the first conductivity type which extend along said two elongated edges (17) of each elongated window (15) and which are separated by said central stripe; implanting a low dose of a second dopant of a second conductivity type along two directions which lie in said plane, and which are substantially simmetrically tilted of a second prescribed angle (A3,A4) with respect to said orthogonal direction (T), to form doped regions of the second conductivity type each comprising two lightly doped elongated channel regions (5) extending under the two elongated edges (17) of each elongated window (15); implanting a high dose of a third dopant of the second conductivity type substantially along said orthogonal direction (T), the insulating material layer (11) acting as a mask, to form heavily doped regions (4) substantially aligned with the edges (17,18) of the elongated windows (15).
机译:制造高密度MOS技术功率器件的方法包括以下步骤:在第一导电类型的轻掺杂半导体材料层(2)的表面上形成导电绝缘栅层(8);在绝缘栅层(8)上形成绝缘材料层(11);选择性地去除绝缘材料层(11)和下面的绝缘栅层(8)以形成具有两个细长边缘(17)和两个短边缘(18)的多个细长窗口(15),从而界定了各自的未覆盖表面条纹(16) )的半导体材料层(2);沿两个方向注入高剂量的第一导电类型的第一掺杂剂,该两个方向位于与所述细长窗口(15)垂直并且与半导体材料层(2)表面正交的平面中,并且基本上与第一方向类似地倾斜相对于正交于半导体材料层(2)表面的方向(T)的规定角度(A1,A2),第一角度(A1,A2)取决于绝缘栅层(8)和绝缘栅层(8)的总厚度。绝缘材料层(11),以防止将第一掺杂剂注入到所述未覆盖的表面条(16)的中央条中,以形成成对的第一掺杂类型的重掺杂的细长的源极区(6),其沿所述两个细长的延伸每个细长窗口(15)的边缘(17),并由所述中央条纹隔开;沿着位于所述平面中的两个方向注入低剂量的第二导电类型的第二掺杂剂,以相对于所述正交方向(T)基本模拟地倾斜第二规定角度(A3,A4)第二导电类型的掺杂区均包括在每个细长窗(15)的两个细长边缘(17)下方延伸的两个轻掺杂细长沟道区(5);基本上沿所述正交方向(T)注入高剂量的第二导电类型的第三掺杂剂,绝缘材料层(11)充当掩模,以形成与边缘(17,)基本对准的重掺杂区(4), 18)的细长窗口(15)。

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