Semiconductor device and back-gate bias application method using silicon on insulator (SOI) substrate

摘要

A method of applying a big-gate bias and a structure thereof in a semiconductor device using a silicon on insulator substrate are disclosed. A semiconductor device comprising a MOS transistor of a first conductivity type and a MOS transistor of a second figure formed separately from a silicon on insulator substrate having a buried insulating layer and an upper semiconductor layer stacked on a lower semiconductor of a first conductivity type. And a second conductive well formed in a first region of the lower semiconductor layer corresponding to the first conductive MOS transistor. Different back-gate bias may be applied to the MOS transistor of the first conductivity type and the MOS transistor of the second conductivity type, respectively.