A semiconductor memory device having a hierarchical bit line structure employing an improved bit line pre-

摘要

The semiconductor memory device includes a main bit line pair MBL and / MBL, a plurality of sub bit line pairs SBL and / SBL, a plurality of selection transistor pairs Qs and / Qs, a plurality of word lines WL, (MC) and a plurality of first precharge circuits (PRL, Qp, / Qp). A plurality of sub bit line pairs are provided corresponding to the main bit line pair. The first and second sub-bit lines of the plurality of sub-bit line pairs are arranged in a straight line in accordance with the main bit line pair. A plurality of select transistor pairs are provided corresponding to a plurality of sub bit line pairs. Each of the plurality of select transistor pairs is connected between a main bit line pair and a corresponding sub bit line pair, and is rendered conductive in response to a predetermined selection signal (BS). The plurality of word lines are arranged to intersect with the first and second sub bit lines of the plurality of sub bit line pairs. The plurality of memory cells are provided corresponding to the intersections of the first and second sub-bit lines of the plurality of sub-bit line pairs and the plurality of word lines. Each of the plurality of memory cells is connected to a corresponding bit line and a corresponding word line. A plurality of first precharge lines are provided corresponding to a plurality of sub bit line pairs. Each of the plurality of first precharge circuits directly precharges the corresponding sub bit line pair to a predetermined precharge potential. Therefore, the potential of the sub-bit line pair is high and certainly reaches a predetermined pre-charge potential.