Semiconductor memory device having hierarchical bit line structure employing improved bit line precharging system

摘要

A semiconductor memory device comprises a main bit line pair, a plurality of subbit line pairs, a plurality of selection transistor pairs, a plurality of word lines, a plurality of memory cells, and a plurality of first precharging circuits. The subbit line pairs are provided in correspondence to the main bit line pair. One and other subbit lines of the subbit line pairs are arranged in straight lines along the main bit line pair. The selection transistors are provided in correspondence to the subbit line pairs. Each of the selection transistor pairs is connected between the main bit line pair and the corresponding subbit line pair, and turned on in response to a prescribed selection signal. The word lines are arranged to intersect with one and the other subbit lines of the subbit line pairs. The memory cells are provided in correspondence to intersection points between one and the other subbit lines of the subbit line pairs and the word lines. Each of the memory cells is connected to the corresponding subbit line and the corresponding word line. The first precharging circuits are provided in correspondence to the subbit line pairs. Each of the first precharging circuits directly precharges the corresponding subbit line pair at the prescribed precharging potential.