SEMICONDUCTOR MEMORY DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE EMPLOYING IMPROVED BIT LINE PRECHARGING SYSTEM

摘要

The semiconductor memory device includes a main bit line pair (MBL, / MBL), a plurality of sub bit line pairs (SBL, / SBL), a plurality of select transistor pairs (Qs, / Qs), a plurality of word lines (WL), and a plurality of memory cells. (MC) and a plurality of first precharge circuits PRL, Qp, / Qp.;A plurality of sub bit line pairs are provided corresponding to the main bit line pairs.;The first and second sub bit lines of the plurality of sub bit line pairs are disposed in a straight line along the main bit line pair.;The plurality of selection transistor pairs are provided corresponding to the plurality of subbit line pairs.;Each of the plurality of selection transistor pairs is connected between a main bit line pair and a corresponding sub bit line pair, and is brought into a conductive state in response to a predetermined selection signal BS. The plurality of word lines are arranged to intersect the first and second sub bit lines of the plurality of sub bit line pairs.;The plurality of memory cells are provided corresponding to the intersections of the first and second sub bit lines of the plurality of sub bit line pairs with the plurality of word lines.;Each of the plurality of memory cells is connected to a corresponding sub bit line and a corresponding word line.;The plurality of first precharge paths are provided corresponding to the plurality of sub-bit line pairs.;Each of the plurality of first precharge circuits directly precharges a corresponding subbit line pair to a predetermined precharge potential.;Therefore, the potential of the sub bit line pair is high speed and reliably reaches a predetermined precharge potential.