Method and apparatus for determining the performance of nets of an integrated circuit design on a semiconductor design automation system

摘要

A technique is described which is generally directed to providing better delay determination for "nets" (equivalent circuits of point-to- point wiring) in integrated circuit designs on a semiconductor design automation system by adapting general RC-mesh networks representing those "nets" to efficient nodal matrix circuit solver techniques which are not inherently suited to general RC-mesh circuits. This is accomplished by "collapsing" the general RC-mesh network into an RC-tree equivalent circuit (network) which can be solved (simulated) by such nodal matrix techniques, thus determining node voltages and waveforms for each of the nodes of the simplified network. After solving the simplified network, the simplified network is re-expanded into its original RC-mesh form, determining the node voltages and waveforms at the re-expanded nodes thereof (eliminated during the collapse of the network) by applying simple circuit analysis techniques. Once all of the node waveforms have been re-constructed for all nodes of the original RC-mesh network, they can be compared against critical threshold voltages to determine net delays to each node of the network. Method and apparatus are described.