Semiconductor memory device having an arrangement to reduce stresses on non-selected ferroelectric capacitors while achieving high integration

摘要

A high integration semiconductor memory device which can reduce stresses placed on non-selected ferroelectric capacitors. A plurality of subblock memory circuits are provided wherein first electrodes forming a plurality of ferroelectric capacitors are respectively provided at first address selection switches, a plurality of other electrodes arranged side by side in the horizontal direction are provided so as to meet at right angles to the first electrodes, and the plurality of ferroelectric capacitors are formed at points where the first electrodes and the other electrodes respectively intersect. Different addresses are respectively assigned to the first address selection lines of the respective subblock memory circuits and common addresses are respectively assigned to the second address selection lines of the plurality of subblock memory circuits, thereby forming a shared address selection circuit. The first address selection line, first switching elements and one second address selection line can be used to develop polarization in the ferroelectric capacitors. Further, the remaining second address selection lines are supplied with such a non- selected potential that a voltage applied to the ferroelectric capacitors reaches substantially half the voltage applied to the selected ferroelectric capacitor. On the other hand, when the first address selection line is brought into a non-selected state and the first switching elements are brought into an OFF state, the plurality of second address selection lines are supplied with such a non-selected potential that the voltage applied to the ferroelectric capacitors reach zero.