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Apparatus for detecting undefined states of a finite state machine (FSM) and resetting the FSM upon detection
Apparatus for detecting undefined states of a finite state machine (FSM) and resetting the FSM upon detection
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机译:用于检测有限状态机(FSM)的未定义状态并在检测到时重置FSM的设备
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摘要
A finite-state machine has combinatorial logic connected to a status memory which receives future state signals from the finite-state machine and sends current state signals to the finite-state machine. The combinatorial logic also receives and generates input and output signals which are external to the finite-state machine. The finite-state machine compares the future state signals to at least one reference level to set an error message to reset the finite-state machine for reliable computing and adjustment.
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