首页> 外国专利> CIRCUIT PERFORMING SQUARE ROOT OPERATION/DIVISION OF BASE 2 BY THREE OVERLAPPED STAGES HAVING ESTIMATED OPERATION

CIRCUIT PERFORMING SQUARE ROOT OPERATION/DIVISION OF BASE 2 BY THREE OVERLAPPED STAGES HAVING ESTIMATED OPERATION

机译:电路通过估计工作的三个重叠阶段对基2进行平方根运算/除法

摘要

PROBLEM TO BE SOLVED: To increase the throughput of a quotient digit without increasing cycle time. ;SOLUTION: The implementation of a base 8 peforms a continuous connection for three partial remainder arithmetic circuit and overlaps three quotient selection circuits(QSLC) 302 to 304. Two carry holding adders 307 estimatingly operate result partial remainders which are found corresponding to each value of -1, 0, +1 of the quotient digit by adding a divisor and the complement of 2. Thus, the critical path composed of an SRT repetition generating a quotient digit becomes shorter.;COPYRIGHT: (C)1997,JPO
机译:解决的问题:在不增加周期时间的情况下增加商位数的吞吐量。 ;解决方案:基数8的实现对三个部分余数的算术电路执行连续连接,并与三个商选择电路(QSLC)302至304重叠。两个进位保持加法器307估计结果结果部分余数,这些结果被发现对应于的每个值。通过添加除数和2的补数来得到商数的-1、0,+ 1。因此,由生成商数的SRT重复组成的关键路径变得更短。;版权所有:(C)1997,JPO

著录项

  • 公开/公告号JPH0969040A

    专利类型

  • 公开/公告日1997-03-11

    原文格式PDF

  • 申请/专利权人 SUN MICROSYST INC;

    申请/专利号JP19960175218

  • 申请日1996-07-04

  • 分类号G06F7/52;G06F7/552;G06F17/10;

  • 国家 JP

  • 入库时间 2022-08-22 03:37:15

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