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HIGH RADIX MULTIPLIER ARCHITECTURE

机译:高基数乘法器体系结构

摘要

PROBLEM TO BE SOLVED: To provide a digital multiplier by which the radix to be dealt with is high and the arithmetic speed is accelerated, and to provide the method therefor. ;SOLUTION: In the case of binary number, this multiplier is composed of a multiplier 1 for generating the three-fold number of multiplicand, adder/ subtracter 11, adder 13, coder 15, multiplexers 3 and 5 and left shifters 7 and 9 consisting of 1st and 2nd paths. Either multiplicand A or 3*A is inputted to either of or both of multiplexers 3 and 5. The coder 15 is internally provided with a table of truth value and applies a control signal to the multiplexers and the shifters corresponding to the value of multiplier B. Corresponding to the value of B, the A or one of multiples of A in the 1st and 2nd paths is selected and shifted to left just for the number decided by the value of B. One of positive or negative values decided by the value of multiplier is allocated to the shifted A or one multiple of A as mentioned above, and the adder adds the values of these two paths and outputs the binary number of answer.;COPYRIGHT: (C)1997,JPO
机译:解决的问题:提供一种数字乘法器,通过该数字乘法器可以处理高的基数并加快运算速度,并提供其方法。 ;解决方案:对于二进制数,此乘法器由一个用于生成三倍被乘数的乘法器1,加法器/减法器11,加法器13,编码器15,多路复用器3和5以及左移位器7和9组成第一和第二路径。将被乘数A或3 * A输入到多路复用器3和5中的一个或两个。编码器15在内部提供真值表,并向多路复用器和对应于乘法器B的值的移位器施加控制信号。对应于B的值,选择A或第一和第二路径中A的倍数之一,并向左移动,仅保留由B的值确定的数字。如上所述,将乘法器分配给移位的A或A的一个倍数,并且加法器将这两个路径的值相加并输出答案的二进制数。; COPYRIGHT:(C)1997,JPO

著录项

  • 公开/公告号JPH09114647A

    专利类型

  • 公开/公告日1997-05-02

    原文格式PDF

  • 申请/专利权人 TEXAS INSTR INC TI;

    申请/专利号JP19960130221

  • 发明设计人 MAHANT-SHETTI SHIVALING S;LEMONDS CARL E;

    申请日1996-05-24

  • 分类号G06F7/52;G06F7/54;

  • 国家 JP

  • 入库时间 2022-08-22 03:32:51

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