Counter module for repeated counting of values in preset bit range

摘要

The single-bit counters (2a-c) are so interconnected that a transmission signal, generated during counting, is fed from one single-bit counter to another one in a following stage. A CPU (5) supplies an instruction for repeated value counting in a region corresp. to a part of the single-bit counters. A register (3) supplies a masking signal for the transmission signal, corresp. to the CPU instruction. A device receivers the transmission signal from one single-bit counter for neutralising counting by a single-bit counter in the following stage of the preset counter.