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- The field effect transistor with a thin barrier layers and a thin, doped layer

机译:-具有薄势垒层和薄掺杂层的场效应晶体管

摘要

This transistor comprises at least a first stack (6) of semiconductor layers - conducting state and at least a second stack (8) of semiconductor layers - conductive, donor of electric charges are superposed and supported by a substrate (2), optionally at least a potential well (12) in the first stack in order to increase the concentration of carriers in this first stack, and at least a potential barrier (18) in the second stack in order to reduce the concentration of carriers in this second stack, a metal grid (g) resting on the second stack in order to modify the concentration of charge carriers in the first stack, two ohmic contacts (s, d) arranged on one of the stacks, on either side of the grid, playing the role of the source and drain.
机译:该晶体管包括至少一个半导体层的第一叠层(6)-导电状态和至少一个第二半导体层的叠层(8)-导电,电荷的供体被衬底(2)(任选地至少为了增加该第一堆中的载流子浓度,在第一堆中的势阱(12),以及为了减少该第二堆中的载流子浓度,在第二堆中至少一个势垒(18),金属栅格(g)搁置在第二个堆栈上以改变第一堆栈中载流子的浓度,两个欧姆接触(s,d)排列在其中一个堆栈上,位于栅格的两侧,起着源和漏。

著录项

  • 公开/公告号DE69211234T2

    专利类型

  • 公开/公告日1997-01-30

    原文格式PDF

  • 申请/专利权人 FRANCE TELECOM FR;

    申请/专利号DE1992611234T

  • 发明设计人 GERARD JEAN-MICHEL FR;FAVRE JACQUES FR;

    申请日1992-07-06

  • 分类号H01L29/778;H01L29/225;H01L29/36;H01L29/205;

  • 国家 DE

  • 入库时间 2022-08-22 03:13:17

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