首页> 外国专利> Inverter gate circuit of a bi-CMOS structure having common layers between fets and bipolar transistors

Inverter gate circuit of a bi-CMOS structure having common layers between fets and bipolar transistors

机译:双CMOS结构的反相器栅极电路,在FET和双极晶体管之间具有公共层

摘要

A semiconductor device comprises a p-type semiconductor substrate, an n-type semiconductor well formed on the substrate and connected to a positive power supply, a p-type semiconductor source formed within the n- type semiconductor well, a p-type semiconductor layer formed within the n- type semiconductor well and having a lower impurity concentration than the p-type semiconductor source, a first gate electrode formed over a region between the p-type semiconductor source and the p-type semiconductor layer through an insulating film, an n-type semiconductor emitter formed over the p-type semiconductor layer within the n-type semiconductor well, a first conductive layer formed over the n- type semiconductor well to connect with said p-type semiconductor source.
机译:一种半导体器件,包括:p型半导体衬底;形成在衬底上并连接到正电源的n型半导体阱;形成在n型半导体阱内的p型半导体源; p型半导体层。形成在n型半导体阱内并具有比p型半导体源低的杂质浓度的第一栅电极,第一栅电极通过绝缘膜形成在p型半导体源和p型半导体层之间的区域上,在n型半导体阱内的p型半导体层之上形成的n型半导体发射极,在n型半导体阱之上形成以与所述p型半导体源连接的第一导电层。

著录项

  • 公开/公告号US5583363A

    专利类型

  • 公开/公告日1996-12-10

    原文格式PDF

  • 申请/专利权人 KABUSHIKI KAISHA TOSHIBA;

    申请/专利号US19920860596

  • 发明设计人 HIROSHI MOMOSE;TAKEO MAEDA;KOJI MAKITA;

    申请日1992-03-30

  • 分类号H01L29/76;H01L29/94;H01L31/062;H01L31/113;

  • 国家 US

  • 入库时间 2022-08-22 03:10:57

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号