A method for the production of an integrated circuit with complementary bipolar transistors and complementary insulating layer - gate - field effect transistors on a common substrate

摘要

Specific impurity concentration regions are used for the simultaneous formation of CMOS devices and complementary bipolar transistors to produce high voltage, high performance bipolar transistors. The last diffusion step for shallow P.sup.+ and N.sup.+ emitter regions and contact regions is performed without a separate diffusion cycle. The formation of the gate oxide at a relatively low temperature is followed immediately by the formation of an undoped polysilicon gate layer. The polysilicon gate layer is doped to a reasonable resistance and also forms a first level interconnect. Phosphorous doped CVD silicon oxide is formed thereover and the top surface is treated with additional phosphorous to produce tapered contact apertures therethrough when etched. A layer of metal is applied and delineated to form contacts to the substrate regions and to form the second level of interconnects.