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High-density programmable logic device in a multi-chip module package with improved interconnect scheme
High-density programmable logic device in a multi-chip module package with improved interconnect scheme
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机译:具有改进互连方案的多芯片模块封装中的高密度可编程逻辑器件
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摘要
A high performance single package multi-chip module multiplies the logic density of the highest density monolithic programmable logic device (PLD). A dual-sided substrate carries multiple prepackaged PLDs on a top side and a field programmable interconnect (FPIC) die on a bottom side. The input/output terminals of the PLDs are interconnected with the FPIC die in a scrambled fashion to reduce signal skew.
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