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Structural Optimization of Multi-Chip Module Composed of Wafer Process Packages to Improve Reliability

机译：由晶片过程包装组成的多芯片模块的结构优化，提高可靠性

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Yasuhiro NAKA; Naotaka TANAKA; Takahiro NAITO;
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年度 2004
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4. Highly Reliable and Low-Cost Multi-Chip Module Composed of Wafer Process Packages [C] . Yasuhiro Naka, Naotaka Tanaka, Takahiro Naito Electronic Components Technology Conference . 2003

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5. Optimization of Board Level Reliability of Microelectronic Packages and Modules [D] . Lohia, Alok Kumar. 2018

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8. Pulsed Laser-Induced Reactive Processing of CVD-Diamond Substrates Under Liquid Ambient: A Process for 3-D Multi-Chip Modules [R] . Schaper, L. W. , Malshe, A. P. , Naseem, H. 1999

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Structural Optimization of Multi-Chip Module Composed of Wafer Process Packages to Improve Reliability

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