CLOCK SYSTEM AND SEMICONDUCTOR DEVICE, AND METHOD FOR TESTING SEMICONDUCTOR DEVICE, AND CAD DEVICE

摘要

PROBLEM TO BE SOLVED: To easily realize a sequential circuit and a clock system, and to reduce the power consumption of the clock system itself by generating a 1f clock with a frequency necessary for a state storage circuit from a 1/2f clock. ;SOLUTION: A clock with a frequency 1/2 of the frequency of a clock, whose pulse width is narrow and used for a state storage circuit 54 constituting a sequential circuit, is inputted from the outside of a semiconductor device. This 1/2f clock is inputted to a clock input terminal, and fetched in the semiconductor device by a clock buffer 51. The fetched 1/2f clock is distributed from the clock input buffer 51 to each part of the semiconductor device, and a clock buffer 52 is provided in the middle for compensating the insufficiency of a driving capability due to the presence of only the clock input buffer 51. A 1f clock generating circuit 53 generates a 1f narrow pulse clock 1f CK with a frequency twice the size of the frequency of the distributed 1/2f clock, and supplies it to a latch circuit 54 constituting the adjacent sequential circuit.;COPYRIGHT: (C)1998,JPO