A programmable timer circuit (18) includes a counter (22) that contains a plurality of sequentially arranged counter stages (22a, 22b). A toggle logic gate (25) is disposed between each sequential pair of counter stages to accept the output signal from the preceding stage and to issue an input signal to the succeeding counter stage. The logic state of the input signal is determined by the logic state of the preceding output signal and the logic state of a program stage signal from an associated program stage. The logic state of the program signal is determined by the state of a fuse (F) associated with the program stage. Selected fuses can be blown by a programming routine includes activating the counter stages that will be active at the desired count and issuing a programming signal to burn the fuse associated with the active counter stage.
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