High frequency noise and impedance matched integrated circuits

摘要

An monolithic integrated circuit comprising a transistor-inductor structure is provided having simultaneously noise matched and input impedance matched characteristics at a desired frequency. The transistor-inductor structure comprises a first transistor Q1 which may be a common emitter bipolar transistor or common source MOSFET transistor Q1, a second optional transistor Q2, a first inductor LE in the emitter (source) of Q1, and a second inductor LB in the base (gate) of Q1. The emitter length lE1, or correspondingly the gate width wg, of Q1 is designed such that the real part of its optimum noise impedance is equal to the characteristic impedance of the system, Z0, which is typically 50Ω. The first inductor LE, provides matching of the real part of the input impedance and the second inductor LB cancels out the noise reactance and input impedance reactance of the structure. The resulting simultaneously noise and impedance matched integrated circuit provides optimal performance. The optimized transistor-inductor structure has particular application to silicon integrated circuits, such as low noise amplifiers and mixer circuits, for wireless and RF circuit applications at 5.8 Ghz, previously reported only for GaAs based circuits. Other basic silicon integrated circuits were optimized at frequencies up to ~12 GHz.