Optimization Technique for Simultaneous Noise and Input/Output Impedance Match of an Integrated 5 GHz CMOS Low-Noise Amplifier

摘要

Based on measured four-pole noise parameters and 2-port scattering parameters, an optimization technique for minimum noise match simultaneously with input and output impedance match was developed for a 2-port network and applied in the design of a single-ended 5 GHz CMOS LNA in a CMOS 0.18-um technology. Explicit formulas for input and output impedance match under minimum noise match were derived and verified in circuit design.