Sampling error prevention circuit of analog / digital converter

摘要

The present invention relates to a technique for converting an analog voltage into a digital signal and outputting it. In the conventional analog / digital converter, when a clock signal supplied to each comparator has a predetermined delay time due to design conditions or other reasons There is a problem in that a sampling error is generated due to sampling of different analog input voltages because the means for solving this problem are not frequently provided.;In order to solve the problem, the present invention provides a D / A converter for converting an analog voltage into a digital value, comprising a plurality of PLL 1 to PLL 8, And a PLL unit 15 for locking the clock signal CK1 supplied to the comparator CP1 and supplying the clock signal CK1 to the comparators CP2-CP8 as clock signals CK2-CK8, respectively.