首页> 外国专利> METHOD OF MAKING A MEMORY FAULT-TOLERANT USING A VARIABLE SIZE REDUNDANCY REPLACEMENT CONFIGURATION

METHOD OF MAKING A MEMORY FAULT-TOLERANT USING A VARIABLE SIZE REDUNDANCY REPLACEMENT CONFIGURATION

机译:使用可变大小冗余替换配置来制造存储器容错的方法

摘要

A method of making a memory fault-tolerant through the use of a variable sizeredundancy replacement (VSRR) circuit arrangement. A redundancy array supportingthe primary arrays forming the memory includes a plurality of variable size redundancyunits (RUs), each of which encompassing a plurality of redundant elements (REs). Theredundant units (RUs) used for repairing faults in the memory are independentlycontrolled. All the redundancy elements (REs) within a repair unit are preferablyreplaced simultaneously. The redundancy elements (REs) in the redundancy unit (RU)are controlled by decoding address lines. The variable size that characterizes thisconfiguration makes it possible to choose the most effective redundancy unit (RU), andin particular, the one most closely fitting the size of the cluster of failures to be replaced.This method significantly reduces the overhead created by added redundancy elements(REs) and control circuitry, while improving the access speed and reducing powerconsumption.Fig. 4a
机译:一种通过使用可变大小来使内存容错的方法冗余替换(VSRR)电路布置。冗余阵列支持形成存储器的主阵列包括多个可变大小的冗余单元(RU),每个单元都包含多个冗余元素(RE)。的用于修复内存故障的冗余单元(RU)是独立的受控。维修单元内的所有冗余元件(RE)最好是同时更换。冗余单元(RU)中的冗余元素(RE)通过解码地址线来控制。表征此的可变大小通过配置可以选择最有效的冗余单元(RU),并且特别是最接近要替换的故障群的大小的那个。该方法大大减少了添加冗余元素所产生的开销(RE)和控制电路,同时提高访问速度并降低功耗消费。图4a

著录项

  • 公开/公告号SG67484A1

    专利类型

  • 公开/公告日1999-09-21

    原文格式PDF

  • 申请/专利权人 INTERNATIONAL BUSINESS MACHINES CORPORATION;

    申请/专利号SG19980000502

  • 发明设计人 TOSHIAKI KIRIHATA;

    申请日1998-03-06

  • 分类号G11C7/00;

  • 国家 SG

  • 入库时间 2022-08-22 02:25:42

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