A programmable interconnect cell array having a floating gate as the gate of a MOS switch transistor that programmably connects or disconnects a node is used in an FPGA. The floating gate 15G of each cell capacitively coupled to the control gate 53 is programmed by Fowler-Nordheim tunneling through the tunneling oxide 31G on the programming / erasing line 41 in the integrated circuit substrate 940, do. At least one tunneling control line (71A, 71B) adjacent and parallel to the programming / erasing line forms a PN junction adjacent the programming / erasing line under the tunneling oxide. Under reverse bias, a deep charge depletion region is formed in the programming / erasing line to prevent tunneling. In this way, the selected cell can be programmed / erased, but the unselected cell is not programmed / erased.
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