METHOD AND DEVICE FOR DESIGNING LAYOUT OF TEST- FACILITATED SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To reduce the total of scan path lengths in the layout design of a test-facilitated semiconductor integrated circuit having plural scan paths.;SOLUTION: After the arrangement of respective cells is determined by an arranging device 102, a node allocating device 106 performs allocation to the respective scan paths of a scan-in terminal, scan-out terminal and scan FF so as to reduce the total of scan path lengths as short as possible, and next, a route optimizing device 107 determines/improves the connection order of scan FF so as to minimize the length of each scan path, and a node exchange device 108 exchanges the scan FF, scan-in terminal and scan-out terminal among the plural scan paths so as to reduce the total of scan path lengths.;COPYRIGHT: (C)2000,JPO