Outline wiring design method and outline wiring design device null of integrated

摘要

PROBLEM TO BE SOLVED: To provide a rough wiring method/and a device with respect to a chip containing various macros. ;SOLUTION: A hierarchical structure for quartering a chip area hierarchically is constituted by recurrently applying a processing for quartering a rough cell higher by one into four rough cells of 2×2 (step S102). The wiring passing capacity of the high-order rough cell is estimated based on wiring passing capacity calculated on the rough cell in respective hierarchy levels by following the hierarchy level from the low-order one to the high-order one (step S103). A condition on the wiring passing capacity of the respective sides of the high- order rough cell is satisfied in the respective hierarchical levels, the rough wiring route of a net, which is obtained in the high-order hierarchy, is succeeded and the rough wiring route of the passing net of the four rough cells of 2×2 is decided by following the hierarchy level from the high-order one to the low- order one (step S104).;COPYRIGHT: (C)1998,JPO