AUTOMATIC LAYOUT AND WIRING DESIGN METHOD FOR INTEGRATED CIRCUIT, AUTOMATIC LAYOUT AND WIRING DESIGN APPARATUS THEREFOR, AUTOMATIC LAYOUT AND WIRING DESIGN SYSTEM THEREFOR, CONTROL PROGRAM AND READABLE RECORDING MEDIUM

摘要

PROBLEM TO BE SOLVED: To shorten the design time by suppressing electro-migration at the stage of layout design in an integrated circuit of a VLSI or the like.;SOLUTION: In the automatic layout and wiring design method, a transition coefficient (signal transition coefficient) regulating operations of a signal between cells is found from logic design verification data created by a logic circuit design apparatus 200, and layout design is performed with the signal transition coefficient as an evaluation reference. When locating cells, the signal transition coefficient between cells is used in addition to a virtual wiring length or a wiring congestion degree to determine the locations of cells, such that power consumption is made uniform within a chip. Besides, a cell block to become a target of location and wiring processing is determined and when performing location processing for the unit of the cell blocks, the cell blocks are divided and merged with the signal transition coefficient between cells and power consumption of each cell as an evaluation reference. When performing rough wiring processing and detailed wiring processing, a wiring route is determined in order from a greatest value of the signal transition coefficient corresponding to a wiring request.;COPYRIGHT: (C)2004,JPO