PHASE LOCKED LOOP WITH IMPROVED LOCK TIME AND STABILITY

摘要

A phase locked loop (PPL) circuit is used to synchronize a local clock frequency with an edge of a reference clock frequency, employing a phase detector (30) to compare the local clock frequency and the reference clock frequency to generate a control signal indicative of the need to increase or to decrease the local clock frequency for phase locking thereof to the reference clock frequency. A voltage controlled oscillator (VCO) (35) is responsive to a signal voltage derived from the control signal to vary the local clock frequency as necessary to achieve phase locking. A loop filter (32) has a reference voltage threshold level which is preprogrammable to enable the loop filter to respond to the control signal by adjusting the signal voltage as a virtual step function toward the programmed reference voltage threshold level before application to the VCO (35), and then cycling up and down in search for a stable control signal voltage to reduce the time necessary to achieve the desired phase locking.