PURPOSE: An inner clock generating circuit suitable for synchronous semiconductor memory device is provided to reduce power consumption and to generate an inner clock accurately synchronized to an external clock by successively the inner clock in a unit delayer and restraining all operation of devices installed in a rear of the unit delayer. CONSTITUTION: A clock buffer(310) converts an external clock with a TTL level provided from a microprocessor or a DRAM controller into a clock with a CMOS level, and outputs the converted clock as a first clock. A main delayer(320) outputs a second clock. A unit delay set(350) receives the first clock, a second clock, and an input clock of the main delayer(320), and generates a phase comparing signal. A period delay set(360-1) generates a period phase comparing signal(T6). A monitoring unit(400) responds to the phase comparing signal and period comparing signals, and restrains an operation of unit delay sets in a period delay set.
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