A synchronous semiconductor memory device having an internal clock signal generation circuit for generating an internal clock signal which is phase-locked with high precision with respect to an external clock signal.

摘要

In an internal clock signal generation circuit, a phase comparator for detecting a phase difference between an external clock signal and an internal clock signal includes a transistor and a capacitance for a signal line for transmitting a clock signal corresponding to the external clock signal, and at the same time, an internal clock signal. And a transistor and a capacitor with respect to a signal line for transmitting a clock signal corresponding thereto. As a result, the rising timing of the signal whose phase is delayed among the signals of the two signal lines is loosened. As a result, the phase difference is enlarged, and the phase comparator 14 can perform the phase comparator with high precision.