DELAY LOOKED LOOP WITH VARYING CLOCK DELAY AND SEMICONDUCTOR MEMORY DEVICE USING DELAY LOOKED LOOP

摘要

Purpose: a delay lock loop of the wide modified clock delay of active frequency range is provided. One memory using delay lock loop provided by. Construction: a phase detectors (311) receive reference clock signal (RCLK) and feedback clock signal (FDCLK) from complementary circuit (341) are postponed. Phase detectors (311) simultaneously generate signal up and down compared with the phase of binary signal. The signal that one feed pump (321) is based on pause detector (311) produces DC voltage (VCON). If generated on signal, VCON is higher than reference level. If generating downward signal, VCON is lower than reference level. One, which becomes delay circuit (331), receives and postpones PCLK, power up signal (PVCCH) and synchronization signal (DLLST) under VCON controls from feed pump (321). Becoming delay circuit (331) has many deferred mounts. After by becoming delay circuit (321), RCLK is the high-level clock signal (ADCLKN) of the variation with different delay times. Delay time is the number depending on operating delay unit. Phase detectors (311) compared with the phase of RCLK and ADCLKN (or FDCLK) and adjust reduce two signals phase difference become delay circuit (331) in deferred mount number. Delay lock loop (301) are used in semiconductor storage, memory is managed to active frequency range, without circuit in changing.