A delay locked loop, semiconductor memory device and method for generating a plurality of delayed clock signals

摘要

A delay locked loop comprises a period locked loop (PL ') having a delay element (14'), the delay element (14 ') having an even number of delay cells (CI1 ~ CI8) connected in the form of a ring and designed to an even number of delayed clock signals (DCLK1 ~ DCLKn), wherein a transition of at least one delayed clock signal of the even number of delayed clock signals (DCLK1 ~ DCLKn) in response to an activated first selection signal is controlled from an even number of first selection signals Transition of the remaining delayed clock signals in response to the at least one delayed clock signal.