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Structure and process for reducing the on-resistance of MOS-gated power devices
Structure and process for reducing the on-resistance of MOS-gated power devices
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机译:用于降低MOS门控功率器件的导通电阻的结构和过程
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摘要
A VDMOS structure with an added n- doping component, and a LOCOS oxide self-aligned to it, at tie surface extension of the drain. The additional shallow n- component permits the body diffusion to be heavier, and hence reduces the risk of latchup.
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