首页> 外国专利> Semiconductor device package including a substrate having bonding fingers within an electrically conductive ring surrounding a die area and a combined power and ground plane to stabilize signal path impedances

Semiconductor device package including a substrate having bonding fingers within an electrically conductive ring surrounding a die area and a combined power and ground plane to stabilize signal path impedances

机译:半导体器件封装,包括衬底,该衬底在围绕管芯区域的导电环内具有接合指,并且具有组合的电源和接地平面以稳定信号路径阻抗

摘要

A semiconductor device package is presented for housing an integrated circuit which includes bonding fingers located within a conductive ring structure and routed to device terminals on an underside surface of the semiconductor device package. The semiconductor device package includes a die area defined upon a planar upper surface, a conductive ring surrounding the die area, and a first set of bonding fingers arranged within the conductive ring. The die area is dimensioned to receive the integrated circuit. The conductive ring may be a power ring or a ground ring. The conductive ring and the first set of bonding fingers are located within a first signal layer adjacent to the upper surface. A set of bonding pads which serve as device terminals reside within a second signal layer adjacent to a planar underside surface. The semiconductor device package also includes a first set of signal traces connected to bonding fingers within the first signal layer, a second set of signal traces connected to bonding pads within the second signal layer, and vias connecting members of the first and second sets of signal traces. The signal traces and vias form signal paths between members of the first set of bonding fingers and corresponding bonding pads which "loop back" upon themselves. The semiconductor device package also includes a combined power and ground plane configured to stabilize the impedances of the "loop back" signal paths.
机译:提出了一种用于容纳集成电路的半导体器件封装,该集成电路包括位于导电环结构内并被布线至半导体器件封装的下表面上的器件端子的键合指。该半导体器件封装包括:限定在平面上表面上的管芯区域;围绕该管芯区域的导电环;以及布置在该导电环内的第一组接合指。管芯区域的尺寸确定为容纳集成电路。导电环可以是电源环或接地环。导电环和第一组接合指位于邻近上表面的第一信号层内。用作器件端子的一组焊盘位于第二信号层内,该第二信号层与平坦的底侧表面相邻。半导体器件封装还包括连接到第一信号层内的键合指的第一组信号迹线,连接到第二信号层内的键合焊盘的第二组信号迹线以及连接第一和第二组信号的构件的通孔痕迹。信号迹线和通孔在第一组接合指的构件与相应的接合垫之间形成信号路径,所述接合垫“环回”其自身。半导体器件封装还包括被配置为稳定“环回”信号路径的阻抗的电源和接地平面的组合。

著录项

  • 公开/公告号US6064113A

    专利类型

  • 公开/公告日2000-05-16

    原文格式PDF

  • 申请/专利权人 LSI LOGIC CORPORATION;

    申请/专利号US19980006356

  • 发明设计人 SCOTT L. KIRKMAN;

    申请日1998-01-13

  • 分类号H01L23/52;

  • 国家 US

  • 入库时间 2022-08-22 01:37:09

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