首页> 外国专利> EXECUTION METHOD FOR PROGRAM VERIFICATION OPERATION, EXECUTION METHOD FOR ERASION VERIFICATION OPERATION, CONTROL CIRCUIT FOR DETECTING TIME, AND FLASH MEMORY DEVICE

EXECUTION METHOD FOR PROGRAM VERIFICATION OPERATION, EXECUTION METHOD FOR ERASION VERIFICATION OPERATION, CONTROL CIRCUIT FOR DETECTING TIME, AND FLASH MEMORY DEVICE

机译:用于程序验证操作的执行方法,用于擦除验证操作的执行方法,用于检测时间的控制电路以及闪存设备

摘要

PROBLEM TO BE SOLVED: To prevent the erroneous trying of program verification operation and the like and the reduction of the speed of a flash memory device when program verification operation and the like are performed after delay previously set, in an execution method of program verification operation and erasion verification operation, a control circuit for a detecting time, and a flash memory device.;SOLUTION: This execution method for program verification operation or erasion verification operation has a step in which a reference memory cell is programmed, a step in which a memory cell is programmed, a step in which a set signal is generated using the contents of the reference memory cell, and a step in which program verification operation or erasion verification operation of a memory cell is started by using the set signal. The device is constituted so as to be provided with a reference page buffer 35d receiving a set start signal and generating the set signal, and plural data page buffers 35a-35c receiving the set signal and storing the contents of plural memory cells.;COPYRIGHT: (C)2001,JPO
机译:解决的问题:在程序验证操作的执行方法中,为了防止错误地尝试程序验证操作等并且在预先设置的延迟之后执行程序验证操作等时降低闪存装置的速度。解决方案:该用于程序验证操作或擦除验证操作的执行方法具有对参考存储单元进行编程的步骤,其中对存储单元进行编程的步骤包括:对存储单元进行编程,使用参考存储单元的内容生成置位信号的步骤,以及通过使用置位信号开始存储单元的编程验证操作或擦除验证操作的步骤。该装置被构成为具有接收设置开始信号并产生设置信号的参考页面缓冲器35d,以及接收设置信号并存储多个存储单元的内容的多个数据页面缓冲器35a-35c。日本特许厅(C)2001

著录项

  • 公开/公告号JP2001176276A

    专利类型

  • 公开/公告日2001-06-29

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP20000339076

  • 发明设计人 YANO MASARU;

    申请日2000-11-07

  • 分类号G11C16/02;G11C16/04;G11C16/06;

  • 国家 JP

  • 入库时间 2022-08-22 01:29:48

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