Driving circuit for driving thin film actuated mirrors in a column in an array of M times N thin film actuated mirrors

摘要

The invented driving circuit consists of both a memory means (170) for storing a video signal in the form of a digitized signal, the video signal having a plurality of line video signals, each of the line video signals being scanned in accordance with a scanning pulse, each of the line video signals being divided into said N number of n-bit data signals and a generator (180) for deriving from the scanning pulse a clock pulse to drive each of said N number of thin film actuated mirrors (40) in the same column as well as for deriving from the scanning pulse a data control signal (LDAC) having a first pulse followed by a second pulse, each of the first and the second pulses having an associated duration, wherein said N number of n-bit data signals is available during the duration of the first pulse and for generating an enable signal, further of plurality of modular circuits (100, 110, 120, 130, 140) of a substantially identical construction, each of the modular circuits (100, 110, 120, 130, 140) being sequentially enabled in accordance with the enable signal to individually drive a predetermined number of actuated mirrors (40) within the same column so that it applies individually to the predetermined number of actuated mirrors (40) a corresponding number of the n-bit data signals, wherein each of the modular circuits (100, 110, 120, 130, 140) includes a decoder (210, 212, 214, 216) for generating a sequential signal through the use of the scanning pulse together with the enable signal, the sequential signal being used to permit the corresponding number of n-bit data signals to be received in sequence, a lock-out section (220, 222, 224, 226) being formed by a system of lock-out circuits (300, 310, 320, 330, 340, 350, 360, 370), serving for conversion of n-bit data signals to analog voltage quantity corresponding to the value of the n-bit data signal, whereby the lock-out circuit (300, 310, 320, 330, 340, 350, 360, 370) comprises a set of input latches (82, 84, 86, 88), each of the input latches serving for temporarily storing one of the corresponding number of n-bit data signals in accordance with the sequential signal, a set of transfer gates (32, 34, 36, 38), each of the transfer gates (32, 34, 36, 38) in synchronization with the transition from the first pulse to the second pulse, simultaneously outputting the n-bit data signal from each of the input latches (82, 84, 86, 88), and an amplifying section (230, 232, 234, 236), having a corresponding number of amplifying means (400, 410, 420, 430, 440, 450, 460, 470), each of the amplifying means (400, 410, 420, 430, 440, 450, 460, 470) amplifying the analog voltage quantity to produce the signal voltage to be applied to each of the predetermined number of the actuated mirrors (40).