3 SELF-ALIGNED 3 PROCESS FLOW FOR SUBMICRON MICROELECTRONICS APPLICATIONS USING AMORPHIZED POLYSILICON

摘要

In a method of implanting phosphorous into an undoped gate polysilicon region formed as part of an integrated circuit structure, the initial MOS structure is a lightly doped drain (LDD) implant, except that the gate polysilicon remains undoped. Steps are made using the prior art. Next, in accordance with the present invention, the dopant is implanted into the source / drain region such that the undoped gate polysilicon is amorphous, thereby removing the polysilicon grain boundaries. A CVD oxide layer is then formed and a CMP step is performed to expose the amorphous gate polysilicon region. A phosphorous oxychloride (POCL ₃ ) layer is then formed on the amorphous gate polysilicon and thermally annealed to inject phosphorus from the POCL ₃ layer into the polysilicon. Then, the POCL ₃ layer is removed.