Properties of yen / p-channel transistors are optimized independently in the CMOS semiconductor device with design features of less 0.25㎛. Removing the second sidewall spacers are possible, that the first side is formed on the sidewall yen channel transistor having a gate electrode on the spacer. Enhyeong jungnong Fig or the ion implantation and subsequent activation heat treatment is performed to form a heavily doped implants. Then, the second sidewall spacer has a first sidewall spacer is used as an ion implantation mask for the implant is doped with a low concentration pihyeong is directly removed from the blood while leaving the transistor channel. Then, the third side wall spacers are formed on the first phase sidewall P-channel gate electrode having a spacer on its side, jungnong the ion implantation and subsequent activation heat treatment is performed also, or to form the implant is doped with a high concentration pihyeong . Embodiments of the first, second, and it is possible that a complete independent control of the 3 by varying the thickness of the sidewall spacer yen / blood of channel transistor channel length.
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