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Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization

机译：工艺变化感知晶体管尺寸，可在动态CMOS中实现多路径负载平衡，以实现时序优化

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Chien-In Henry Chen; Kumar Yelamarthi;
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年度 2008
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1. Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization [J] . Kumar Yelamarthi, Chien-In Henry Chen Journal of Computers . 2008,第2期

机译：处理变化的变化意识晶体管，用于动态CMOS中多路径的负载平衡以进行定时优化
2. Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations [J] . Kumar Yelamarthi, Chien-In Henry Chen VLSI Design . 2010,第SP期

机译：动态CMOS负载平衡和时间优化算法中的路径导向，可最大程度地减少过程变化带来的延迟不确定性
3. Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations [J] . KumarYelamarthi, Chien-In HenryChen VLSI Design . 2010,第3期

机译：动态CMOS负载平衡和时间优化算法中的路径导向，可最大程度地减少过程变化带来的延迟不确定性
4. Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization [C] . Kumar Yelamarthi, Chien-In Henry Chen International Symposium on Quality Electronic Design . 2007

机译：动态CMOS中多路径负载平衡的晶体管尺寸，以进行定时优化
5. Critical ALU path optimization and implementation in a BiCMOS process for gigahertz range processors. [D] . Ernest, Matthew Wayne. 2002

机译：千兆赫范围处理器的BiCMOS关键ALU路径优化和实现。
6. Use of a Multiplexed CMOS Microarray to Optimize and Compare Oligonucleotide Binding to DNA Probes Synthesized or Immobilized on Individual Electrodes [O] . Karl Maurer, Nina Yazvenko, Jodi Wilmoth, 2010

机译：使用多路CMOS芯片优化和比较寡核苷酸与DNA探针的结合或将其固定在单个电极上
7. Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization [O] . Kumar Yelamarthi, Chien-in Henry Chen 2008

机译：工艺变化感知晶体管尺寸，可在动态CMOS中实现多路径负载平衡，以实现时序优化

Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization

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