FERROELECTRIC MEMORY DEVICE HAVING BIT LINE STRUCTURE CONSISTING OF DEPLETION TRANSISTOR

摘要

PURPOSE: A ferroelectric memory device having a bit line structure consisting of a depletion transistor is provided to more improve the degree of integration than a structure in which a bit line and an active line are separated. CONSTITUTION: The ferroelectric memory cell including a ferroelectric capacitor, an enhancement type transistor, a word line(WL) and a bit line(BL) further includes first and second active areas(A1,A2). The ferroelectric capacitor is connected the drain of the enhancement type transistor. The word line selects the enhancement type transistor. The bit line transmits a data received from the enhancement type transistor through the word line to a sense amplifier(S/A). The first active area is connected to a neighboring cell, and the gate of a depletion type transistor is formed thereon to form the bit line. The second active area is close to the first active area, and gates(N0-N15) of the enhancement type transistor are formed thereon. The word line is connected to the gate(D0-D15) of the depletion type transistor and the gate of the enhancement type transistors.