首页> 外国专利> TIME DEPENDENT DIELECTRIC BREAKDOWN TEST PATTERN AND METHOD FOR TESTING TDDB OF MOS CAPACITOR DIELECTRIC

TIME DEPENDENT DIELECTRIC BREAKDOWN TEST PATTERN AND METHOD FOR TESTING TDDB OF MOS CAPACITOR DIELECTRIC

机译:时间相关的介电击穿测试模式及测试MOS电容器介电TDDB的方法

摘要

Reduce the time it takes to test accordingly meurosseo This line is also used in measurement equipment time required for testing can reduce the measurement cost, but also improve the precision of the measurement results from the statistical aspects meurosseo get a larger number of test data at the same time to provide a TDDB test pattern, and using the same MOS capacitor dielectric film TDDB test way. The present invention TDDB test patterns to an aspect of the MOS capacitor and the MOS transistors and the MOS capacitor and the plurality of unit test pattern cell configured to operate the MOS transistor in the fuse for controlling and, each of the unit test pattern cell Moss and a first voltage supply for applying a stress voltage at the same time to the capacitor and MOS transistor, and measuring a change of the total drain current of the plurality of unit test pattern cell in succession to measure the total break-down time of the plurality of unit test pattern cell of: (VFN voltage Forcing node) and the current meter and each MOS transistor of said plurality of unit test pattern cell ammeter and said first voltage supply and a plurality of voltage polsing nodes, each located between the fuse of each unit of the test pattern cell drain current measurement nodes, each located between the drain stage (C drain urrent Measuring Node: including DCMN) and, a second voltage supply for applying a voltage to the drain terminal of the MOS transistor is characterized by configured.
机译:减少相应的测试时间meurosseo这条线还用于测量设备中测试所需的时间,可以降低测量成本,还可以从统计方面提高测量结果的精度meurosseo在获得大量测试数据时同时提供TDDB测试图案,并采用相同的MOS电容器介电膜TDDB测试方式。本发明的TDDB测试图案涉及MOS电容器和MOS晶体管以及MOS电容器和多个单元测试图案单元的一个方面,所述多个单元测试图案单元被配置为操作熔丝中的MOS晶体管以控制并且每个单元测试图案单元Moss第一电压源,用于同时向电容器和MOS晶体管施加应力电压,并依次测量多个单元测试图案单元的总漏极电流的变化,以测量该单元测试图案单元的总击穿时间。 (VFN电压强制节点)的多个单元测试图案单元以及所述多个单元测试图案单元电流表的电流表和每个MOS晶体管以及所述第一电源和多个电压极化节点,每个均位于测试图单元的每个单元的漏极电流测量节点,每个都位于漏极级(C漏极电流测量节点:包括DCMN)和用于应用的第二个电源之间通过配置来表征向MOS晶体管的漏极端子施加电压。

著录项

  • 公开/公告号KR100282432B1

    专利类型

  • 公开/公告日2001-02-15

    原文格式PDF

  • 申请/专利权人 NULL NULL;

    申请/专利号KR19990000568

  • 发明设计人 김하중;

    申请日1999-01-12

  • 分类号H01L21/66;

  • 国家 KR

  • 入库时间 2022-08-22 01:12:28

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