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Method and apparatus for selecting the next instruction in a superscalar or ultra-long instruction wordcomputer with N-branches

机译:在具有n个分支的超标量或超长指令字计算机中选择下一指令的方法和装置

摘要

In a computer capable of executing a superscalar or very long instruction word instruction, the computer may, when compiling multiple primitive operations that can be executed in parallel into a single instruction having multiple parcels, where each parcel corresponds to one operation. The invention is directed to an improved instruction cache that stores all potential subsequent instructions and a method for selecting subsequent instructions if some possible execution branch can occur and must be evaluated. All branch conditions and all addresses of potential subsequent instructions of one instruction are duplicated and stored in the instruction cache. All potential subsequent instructions are stored in the same block of the instruction cache with the next address and the individual instructions are specified by a duplicated offset address. In addition, by dividing the instruction cache into small caches and storing one parcel in each small cache, each parcel can be executed quickly and autonomously. At the same time, all branch conditions are evaluated in parallel and all offset addresses are decoded in parallel to determine the next instruction. Only after the control flow or branch taken, or after a subsequent or next instruction has been determined, the result of the branch is stored and the decoded address is used to late select the next instruction from the instruction cache.
机译:在能够执行超标量或非常长的指令字指令的计算机中,当将可以并行执行的多个基本操作编译为具有多个宗地的单个指令时,该计算机可以将每个宗地对应于一个操作。本发明针对一种改进的指令高速缓存,其存储所有潜在的后续指令,以及一种用于在可能发生执行分支并且必须对其进行评估的情况下选择后续指令的方法。复制一条指令的所有分支条件和所有可能的后续指令的地址,并将其存储在指令高速缓存中。所有可能的后续指令与下一个地址存储在指令高速缓存的同一块中,并且各个指令由重复的偏移地址指定。另外,通过将指令高速缓存划分为小高速缓存并在每个小高速缓存中存储一​​个宗地,可以快速且自主地执行每个宗地。同时,并行评估所有分支条件,并并行解码所有偏移地址以确定下一条指令。仅在采取控制流程或分支之后,或者在确定了下一条或下一条指令之后,才存储分支的结果,并使用解码后的地址从指令高速缓存中后期选择下一条指令。

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