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Manufacture of FET transistor with elevated source and drain regions and minimal channel length, overlaps regions of differing dopant levels at each end of gate

机译:具有增加的源极和漏极区以及最小的沟道长度的FET晶体管的制造,在栅极的每一端与不同掺杂水平的区域重叠

摘要

A gate structure is constructed on the substrate. Near one end of this, a region is doped to a first concentration. A second doped region is formed at a second concentration, overlapping the first. Yet a third doped region is formed, overlapping the second, and having a third doping level differing from the others. The raised drain includes the third region. The second dopant concentration is lower than the third.
机译:在基板上构造栅极结构。在此附近,一个区域被掺杂到第一浓度。第二掺杂区以第二浓度形成,与第一浓度重叠。形成第三掺杂区,与第二掺杂区重叠,并且具有与其他掺杂区不同的第三掺杂水平。凸起的漏极包括第三区域。第二掺杂剂浓度低于第三掺杂剂浓度。

著录项

  • 公开/公告号DE10031624A1

    专利类型

  • 公开/公告日2001-03-08

    原文格式PDF

  • 申请/专利权人 HYUNDAI ELECTRONICS INDUSTRIES CO. LTD.;

    申请/专利号DE2000131624

  • 发明设计人 HO LEE JUNG;

    申请日2000-06-29

  • 分类号H01L21/336;

  • 国家 DE

  • 入库时间 2022-08-22 01:09:45

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