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Manufacture of FET transistor with elevated source and drain regions and minimal channel length, overlaps regions of differing dopant levels at each end of gate
Manufacture of FET transistor with elevated source and drain regions and minimal channel length, overlaps regions of differing dopant levels at each end of gate
A gate structure is constructed on the substrate. Near one end of this, a region is doped to a first concentration. A second doped region is formed at a second concentration, overlapping the first. Yet a third doped region is formed, overlapping the second, and having a third doping level differing from the others. The raised drain includes the third region. The second dopant concentration is lower than the third.
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