Synchronous memory device with programmable write cycle and data write method using the same

摘要

A synchronous memory device capable of performing write operation with a programmable write cycle, and a data write method using the synchronous memory device. The synchronous memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, a precharge circuit for precharging a data input/output line which transmits data to be written to the memory cells, with a predetermined voltage level, and a column selection circuit for writing the data transmitted to the data input/output line to a selected memory cell, in response to activation of a column selection signal. The activation cycle of the column selection signal is determined according to the write cycle modes programmed in a mode register set. The write cycle modes can be programmed in the mode register set with system clock frequency information, so that the number of data write operations per clock cycle can be varied. Thus, a maximum operating speed of a system is not restricted by the data write period of time of the memory device.